Designing Dsp Algorithm with the Virtex-4 Xtremedsp Slice

Finite impulse response (FIR) filter is the key functional block in DSP (Digital Signal Processing) designs and nearly always form the starting point for analyzing an architecture. This paper contains a new filter architecture, along with FPGAVirtex-4 (Xilinx) and XtremeDSP (DSP48) slice. The XtremeDSP slice is a high performance multiplier and arithmetic unit with great flexibility that can form the building block of DSP algorithms implemented in FPGAs. Traditional adder-tree approach limited the performance and extensibility of given filter implementation. By using adder-chain style of implementation these limitations are lifted. A novel approach in both design and implementation of digital FIR filter using the DSP system element of Virtex-4 (Xilinx) architecture – XtremeDSP (DSP48) slice is presented. Embedded nature of the XtremeDSP slice has a radical impact on reducing the power consumed by high-speed multiply and add function.